irrigation_system.v — Spartan-6 XC6SLX9
IDLE
Code
Constraints
Board Info
Sensor
irrigation_system.vVerilog HDL
constraints.ucfUCF Pin Map
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🔲 FPGA Device
FamilySpartan-6
DeviceXC6SLX9
PackageTQG144
Speed Grade-3
Logic Cells9,152
Flip-Flops11,440
I/O Pins102 (user)
Clock100 MHz
ToolXilinx ISE 14.7
BitstreamNot generated
📌 Pin Assignments
clk
LOC: V10
100 MHz Osc
rst
LOC: C9
Push Button
soil
LOC: T10
Sensor AO
pump
LOC: U16
Relay Drive
led_green
LOC: U18
LD0 Pump ON
led_red
LOC: M14
LD1 Pump OFF
📊 Resource Utilization
Slice LUTs12 / 5765 (0%)
Flip-Flops28 / 11440 (0%)
IOBs6 / 102 (6%)
TimingMET — 98.4 MHz
StatusNot programmed
Soil Moisture Sensor
Moisture Level50%
0 — Dry100 — Wet
Auto-cycle test
FPGA Threshold
Dry/Wet boundary50
soil_s: 1'b0 (DRY)
Component Map
Q1 NPN BC547 Transistor
R1,R2,R3 220Ω Resistors
M1 DC Motor (Water Pump)
D1 Green LED — Pump ON
D2 Red LED — Pump OFF
FPGA Automatic Irrigation — Circuit Schematic
100%
+5V VCC GND SOIL SENSOR 50% AO ● GND ● VCC S1 AO FPGA U1 Xilinx Spartan-6 XC6SLX9-3TQG144 CLK: 100 MHz VCC A0 GND pump led_g led_r NOT PROGRAMMED U1 — Spartan-6 Controller R1 220Ω NPN BC547 C B E Q1 M PUMP + OFF M1 — DC Motor R2 220Ω A K D1 GREEN R3 220Ω A K D2 RED SCHEMATIC FPGA Irrigation System Spartan-6 XC6SLX9-3TQG144 EXTC MPL — Sem VI 2026 LEGEND VCC +5V GND Signal Active
SPARTAN-6 FPGA DEVELOPMENT BOARD Xilinx XC6SLX9-3TQG144 | 9K Logic Cells | 100 MHz Clock X XILINX SPARTAN-6 XC6SLX9 ▲1 XC6SLX9-3TQG144 XTAL 100 MHz CLK OSC JTAG/USB PROGRAMMER PROG LED PWR BOARD LEDs LD0 PUMP ON LD1 PUMP OFF LD2 CLK OK LD3 DONE SWITCHES OFF SW0 soil ← click OFF SW1 RST BTN0 SENSOR I/O HEADER soilpump led_gled_r GNDVCC CLKRST T10U16 U18M14 PMOD JA GPIO Expansion LDO REG 3.3V / 1.0V POWER REG CAPS BOARD STATUS NOT PROGRAMMED soil = 1'b1 (WET) VCC +3.3V GND
Output
Waveformt=0
soil
1'b1
pump
1'b0
led_green
1'b0
led_red
1'b1
Console
[0ns]Spartan-6 simulator ready.
[--]Program FPGA then Run.
Idle
Verilog HDL · Xilinx ISE 14.7
t = 0 ns
Board: NOT PROGRAMMED
FPGA Irrigation Simulator v3.0 — Spartan-6

⚡ Xilinx ISE 14.7 — Program FPGA Device

📄
Parse Verilog HDL
irrigation_system.v
--
🔧
Synthesis (XST)
RTL → LUT primitives
--
🗺️
Translate & Map
LUTs → Spartan-6 slices
--
📐
Place & Route (PAR)
Route 6 I/O, 12 LUTs
--
💾
Generate Bitstream
irrigation_system.bit
--
📡
Program Device (JTAG)
Downloading to XC6SLX9...
--
> Xilinx ISE 14.7 iMPACT Console
> Target: XC6SLX9-3TQG144
> Ready. Press Build & Program...
Ready to program